/*
 * @[H]:  Copyright (c) 2021 Phytium Information Technology, Inc. 
 * 
 *  SPDX-License-Identifier: Apache-2.0. 
 * 
 * @Date: 2021-08-03 22:42:48
 * @LastEditTime: 2021-08-05 08:58:21
 * @Description:  Description of file
 * @Modify History: 
 * * * Ver   Who        Date         Changes
 * * ----- ------     --------    --------------------------------------
 */
#ifndef DRIVERS_FPCIE_DMA_H
#define DRIVERS_FPCIE_DMA_H

#ifdef __cplusplus
extern "C"
{
#endif
#include "ft_types.h"

#define DMA_XFER_START (0x01 << 0)
#define DMA_READ (0x00 << 1)
#define DMA_WRITE (0X01 << 1)

#define DMA_CHANNEL_READ_DONE (0x01 << 0)
#define DMA_CHANNEL_WRITE_DONE (0x01 << 1)
#define DMA_CHANNEL_READ_ERROR (0x01 << 8)
#define DMA_CHANNEL_WRITE_ERROR (0x01 << 9)

#define DMA_CHANNEL_READ_DONE_ENABLE (0x01 << 0)
#define DMA_CHANNEL_WRITE_DONE_ENABLE (0x01 << 1)
#define DMA_CHANNEL_READ_ERROR_ENABLE (0x01 << 8)
#define DMA_CHANNEL_WRITE_ERROR_ENABLE (0x01 << 9)

    struct FPcieDmaDescriptor
    {
        volatile u64 axi_base_address;           /* 0x00 */
        volatile u32 axi_address_phase_controls; /* 0x08 */
        volatile u64 pcie_base_address;          /* 0x12 */
        volatile u64 pcie_tlp_header_attributes; /* 0x20 */
        volatile u32 transfer_control;           /* 0x28 */
        volatile u8 axi_bus_status;              /* 0x32 */
        volatile u8 pcie_bus_status;             /* 0x33 */
        volatile u8 channel_status;              /* 0x34 */
        volatile u8 reserve;                     /* 0x35 */
        volatile u64 next_descriptor;            /* 0x36 */
    } __attribute__((packed)) __attribute__((aligned(128)));

#ifdef __cplusplus
}
#endif

#endif // !